Design of a High Frequency Dual Modulus Prescaler using Efficient TSPC Flip Flop using 180nm Technology

A high speed efficient TSPC flip-flop divide-by-16/17 dual modulus prescaler is proposed. The efficient (proposed) TSPC flip-flop with split path not only reduces the clock load and decrease power but also increases the speed of operation. The speed of the precaler can improve in two aspects. First is by adopting a new pseudo divide-by2/3 prescaler, the minimum working period is reduced by half a NOR gate’s delay. Second is by changing the connection of TSPC D-Flip-flops, the minimum working period is reduced by half an inverter’s delay. The proposed circuit is capable of operating up to 1.8GHz and is implemented in 5V, 0.18um CMOS technology. Simulations and designs are performed on Cadence Virtuoso and Spectre tools using UMC 0.18um technology.